数字验证工程师/Digital Verification Engineer
工作性质：全职
工作地点：厦门市
发布日期：常年招聘
截止日期：常年招聘
招聘人数：2
薪水：年薪25-50万
学历：本科以上
语言能力：良好英语能力
简历语言：中文/英文
职工福利：五险一金、节日福利、年终奖金、不定期培训、有助技术成长、公司前景好、老板Nice

职位描述：
1. Independent SoC verification .
2. Responsible for digital module level, and system level verification.
3. Responsible for golden models and micro-architecture using UVM
4. Make verification plan with high coverage and build verification environment.
5. Generate random test vector.
6. Simulate gate-level netlist with timing parameters.
7. Post simulation and functional pattern generation for testing.
8. Support ASIC implementation.
9. Support the FPGA engineer to build and debug the FPGA verification environment.
10. Support software and system productions.
11. Write verification plan documents.
任职要求：
1. Electrical engineering bachelor degree or above, 3 years or above experience.
2. ASIC design verification and implementation flow knowledge.
3. Familiar with digital verification flow.
4. Proficient in coverage model, random constrained vector generated verification methodology (UVM).
5. Familiar with Verilog/SystemVerilog/OOP.
6. Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
7. Have ability of writing TCL/Shell/perl/makefiles script.
8. Experience in crafting testbench environments for block and system level verification.
9. Strong debugging and analytical skills.
10. Good knowledge to UPF and low power verification (for example VCLP, VerdiPA and VCS-NLP).
11. Good programming in Perl/Python, TCL and Shell programming.
12. Having experience in mix signal simulation is preferred.
其他要求：
1、 Strong self-study ability, ability to analyze and solve problems independently.
2、 Good team work and communication skills.
3、 Good English documents reading and writing skills.